● Rapid development of semiconductor packaging technology
The rapid development of technologies such as AI and HPC is raising the demand for semiconductor performance and energy efficiency. Existing packaging technologies have become difficult to meet the needs of the AI era, providing an opportunity for advanced semiconductor packaging technologies to gain attention.
This has led major semiconductor companies to invest heavily in the sector, and Broadcom recently announced new advances in advanced packaging technology.
[Broadcom Announces First 3.5D F2F Packaging Technology to Meet AI Computing Demand]
Broadcom unveiled its 3.5D eXtreme Dimensity System-in-Package (XDSiP) platform through its official website. It is the industry’s first 3.5D F2F packaging technology, integrating over 6000 mm² of silicon and up to 12 HBM memory stacks into a single package. The technology meets the high efficiency and low power needs of AI chips.
Broadcom emphasized the need for 3D stacking to achieve better form factors, power efficiency, and cost-effectiveness with the advent of new and increasingly complex large-scale language models (LLMs). The 3.5D integration technology combines 3D silicon stacking and 2.5D packaging to become the preferred technology for next-generation XPUs over the next decade.
Broadcom’s F2F technology connects the upper metal layer directly, providing a dense and reliable connection with minimal electrical interference and excellent mechanical strength.
Broadcom said it worked closely with customers to develop the 3.5D XDSiP platform, leveraging TSMC’s technology and the tools of its EDA partners. The platform stacks chip components vertically to allow them to choose the best manufacturing process for each component, reduces interposer and package size, and dramatically improves performance, efficiency, and cost.
Broadcom is currently developing more than five 3.5D products, with most consumer AI customers adopting the 3.5D XDSiP platform and planning to start mass production in February 2026.
[AI boom sparks innovation in high-tech packaging]
The rapid rise of AI is driving the emergence of advanced packaging technologies and attracting large investments from many companies. In addition to Broadcom, TSMC, Samsung Electronics, ASE, and Intel are actively developing these technologies.
TSMC’s CoWoS advanced packaging technology is gaining significant attention in the market, and the company is also investing heavily in developing SoIC packaging technology. TSMC has integrated the packaging process into a 3D fabric system consisting of SoIC series (3D stacking technology), CoWoS series, and InFO series.
SoIC is a next-generation packaging innovation introduced in April 2018, combining CoWoS and Wafer-on-Wafer (WoW) stacking technologies. This allows TSMC to produce 3D ICs directly for customers.
The technology began small-scale production in 2022, with TSMC planning to expand its production capacity by more than 20 times by 2026. In addition, a November report showed that TSMC has secured 30 hectares of land at the southern Taiwan Science Park, creating an advanced supply chain zone focused on advanced packaging, which will support CoWoS/SoIC production at Chiayi (AP7) and Tainan (AP8) facilities.
In July, Samsung Electronics announced that it was developing 3.3D advanced packaging technology for AI semiconductor chips. Samsung’s concept is to vertically stack its GPUs (AI computing chips) and LCC caches into a single unit connected to HBM memory. Silicon bridge chips connect the dies directly, and instead of the more expensive silicon interposer, they use transparent media for the copper RDL redistribution layer.
This design reduces production costs by 22 percent without affecting chip performance. In addition, Samsung plans to integrate panel-level packaging (PLP) into 3.3D technology. A large rectangular substrate that will replace a limited area of a circular wafer will further improve packaging efficiency.
In March, ASE announced a new Chiplet Interconnect technology to address the diverse chip integration design and advanced packaging needs required by AI development.
The technology uses microbump technology and new metal stacking, which significantly reduces the chip-to-wafer interconnect gap. ASE said enhancing chiplet-level interconnect technology could extend its applications to AI chips, mobile application processors, MCU microcontrollers and other key chips.
In January, Intel announced that its 3D Foveros advanced packaging technology has entered the mass production phase at its Fab 9 facility in New Mexico, the United States. Foveros technology integrates horizontal and vertical interconnects that stack memory over active components to improve latency and bandwidth.
The technology divides the product into smaller chiplets or tiles, stacking I/O, SRAM and power transfer circuits on the base die and high-performance logical chiplets on top.
Foveros enables ultra-low power, high-density chip interconnects, minimizes partitioning overhead, and reasonably selects the right chip process for each block. This improves cost and performance, simplifies SKU generation, and reduces time to market.