● Trends in next-generation memory

1. DRAM – Transition to 1c Process

• 1b is 12 nano or 13 nano early, 1c is 11 nano. The last roadmap is 1d 10 nano
• Expect 1b to exceed 1a weight from 3Q24
• 1b will be the main product by the second half of 25
• The biggest difference in going to 1c is the increase in EUV process number: Micron uses 1st step of EUV process from 1c. Samsung Electronics increases the number of steps when converting to 1b, and SK Hynix increases the number of steps when converting to 1c

1. HKMG

• You need to use HKMG to improve speed
• Until now, some products such as DDR and LPDDR have been using HKMG, but it will be applied regardless of application from 1c
• It is advantageous to use ruthenium or molybdenum as the conductor of the wiring itself rather than polysilicon or tungsten

1. 3D NAND

• NAND’s main products are 176 or 162 layers
• From the 100th tier, 2nd tier, and 300th tier, 1 road map
• Not long ago, Samsung Electronics announced that it will mass-produce the V9. This is 2yy 286 level
• The first application of Cell On Peri called COP was 176 layer, then 236 layer, and the third application of COP was 286 layer
• Micron is CUA, CMOS Under Array, SK Hynix is PUC, and the name of Peri Under Cell is the same

1. Direct bonding (hybrid bonding)

• Direct bonding (hybrid bonding) will be applied to all units from 400 units
• Using two wafers minimizes the impact of heat treatment and allows TRs to make multiple designs and do it properly
• Improving yield is a problem, but when it is resolved, it is a much more advantageous phase, so the adoption of direct bonding provides tremendous benefits for Copper Bonders, CMP equipment, and inspection equipment
• In particular, inspection equipment that aligns and checks if it’s stuck properly is a huge benefit

1. cryogenic etching

• Starting with Ram Research, etched as a single stack with the deepest 143-layer product on the market
• Samsung has a technology that can etch 150-speed gates at once, and if you go to the triple house, it becomes 430-unit. Then 3xx becomes a skip
• Introduction of cryogenic etching equipment. Supply already started at TEL. Partially applied at 236th stage, 286th stage. Extended application
• If it’s an additional set-up, you can go to 160-170 stages
• Samsung Electronics will be ahead for a certain period of time due to the contractual relationship and recipe contract terms. Subsequently, it will be expanded

● Cryogenic etching and hybrid bonding

• Currently commercially available 3D NANDs have 150 to 170 channel holes that can be pierced at once
• Layer 2 (double stack) and 3 (triple stack) cell layers with channel holes
• If Ram Research’s 200-layer etching succeeds, more than 400 layers can be stacked with only a double stack
• Cryogenic etching is necessary because chemical reactivity is lowered when the temperature of the etching environment is low, so more precise etching is possible
• The temperature at which cryogenic etching is implemented in the mass production process is -63°C. The lower the temperature, the higher the etching performance, but given the surrounding chemical reactions and production efficiency, -63°C is the most suitable for mass production
• In the future, NAND will reach 400 to 1000 stages faster than 200 to 400 stages
• In the future, NAND will become important not only in etching technology but also in bonding technology
• Currently, NAND is made on a single wafer by cell and peripheral circuitry for cell driving. Since the ferry is located below the cell, it is called ‘Perry Under Cell (PUC)’, ‘Cell On Perry (COP)’ and so on.
• As the number of cell stacks increases, the burden on the ferries in the current method increases. Accordingly, a hybrid bonding technology that manufactures cells and ferries on different wafers and connects each wafer is attracting attention
• Samsung Electronics has confirmed that it will adopt cryogenic etching technology and hybrid bonding technology from V10, where 400 steps are adopted
• Cryogenic etching equipment looks like RAM Research and TEL are competing, and hybrid bonding equipment is ahead of BESI
• When hybrid bonding is applied to this, it has adopted to apply full-cut dicing through femtosecond laser grooving equipment. Starting with the femtosecond laser, Eotechnics will lead the order of equipment, ahead of disco’s technology

https://zdnet.co.kr/view/?no=20240823142400

●Next-generation semiconductor trends and biotechnics

1. LLW(Low Latency Wide I/O)

• Market May Be Shaped As Main Memory Of Mobile On-Device AI
• Apple also reportedly selected the grooving equipment supplied to TSMC because of LLW. LLW was also used in Samsung Electronics’ Galaxy S24
• On-device AI will increase the usage of Wide I/O memory and increase Q. Wafer should be thinned due to light, thin, short and small size

1. BV NAND(Bonding Vertical NAND)

• The direction of increasing the number of layers through wafer fit because V NAND cannot increase the number of layers indefinitely by deposition
• The thickness of individual wafers should be thinned and technology will be applied from NAND specifications scheduled to be released in 2025
• Technology needed for Samsung Electronics’ roadmap for 1000th tier and SK Hynix’s roadmap for 400th tier and above
• Starting with Samsung Electronics’ NAND V10, it has been confirmed to use a mixture of stealth dicing and grooving. In May 2024, we will place an order for test equipment at the same time to ASM and conduct a test until November to determine M/S in 2025

1. 3D DRAM

• DRAM, like NAND, needs to be stacked in 3D form to achieve high performance
• Traditional planar transistors allow vertical CAT to extend transistor Q in the form of columns
• High possibility of vertical stacking and ALD technology being used due to the limitation of miniaturization
• Lamination with 3D DRAM will eventually lead to thinner wafer thickness and open areas of laser full-cut equipment

1. Hybrid bonding

• Even after HBM4, hybrid bonding will become a trend due to interspecies bonding, 3D SoC, etc